1. Field of the Invention
The present invention relates to a solid-state imaging device and a method of manufacturing the solid-state imaging device, and more particularly, to a solid-state imaging device capable of suppressing a leak current of a CMOS (complementary metal oxide semiconductor) type solid-state imaging device constructed with a semiconductor and reducing noise at a low luminance time or dark time, and method of manufacturing the solid-state imaging device.
2. Description of the Related Art
A CMOS (complementary metal oxide semiconductor) type solid-state imaging device (hereinafter, sometimes referred to as a CMOS type imaging device) may be driven at a low voltage level and may easily satisfy a requirement of a high pixel density in terms of power consumption and a requirement of a high reading speed.
Recently, due to these characteristics, the CMOS type image capturing devices have been used in digital single lens reflex cameras necessitating a high image quality and a professional image capturing apparatuses as well as small-sized personal apparatuses such as mobile phones attached with cameras. In addition, the CMOS type image capturing device has been attracted attention as a high performance image capturing device that is a substitute for a CCD (charge coupled device) of the related art.
In the related art, it is said that in the image capturing device, noise may be easily introduced in an image at a dark time or a low luminance time. Due to the unfavorable result of the comparison with a silver salt camera, some users have refused to use the image capturing devices. Therefore, noise reduction in the image capturing device has become an issue.
Therefore, a technology for reducing noise by suppressing a leak current at a dark time of a low luminance time in photodiodes and floating diffusions included in the CMOS type image capturing device has been considered to be important.
FIG. 1 illustrates an example of a configuration of a CMOS type image capturing device including a floating diffusion in the related art. In general, the floating diffusion FD is disposed opposite to a photodiode PD with a transfer gate TG for transferring charges interposed therebetween, which is constructed with Poly-Si (polysilicon) or the like. An impurity diffusion layer having the same conduction type as that of the photodiode PD is formed at the position where a transfer gate TG for transferring charges is interposed (refer to Japanese Unexamined Patent Application Publication No. 2001-028433).
Among the CMOS type image capturing devices, in a CMOS type image capturing device having the rolling shutter scheme, the floating diffusion is used as a signal charge reading element. On the other hand, in a CMOS type image capturing device having the global shutter scheme, the floating diffusion is used as an element of storing the signal charges until the reading is performed in addition to the reading element (refer to Japanese Unexamined Patent Application Publication No. 2006-311515).
Now, the rolling shutter scheme and the global shutter scheme are described.
The CMOS type image capturing devices may be classified into two types, the rolling shutter scheme (sometimes referred to as a focal plane shutter scheme or a line exposure scheme) and the global shutter scheme according to a difference of a concurrency in an accumulation time interval (or an exposure time interval) of signal charges photo-electrically converted by the photodiodes (refer to Japanese Unexamined Patent Application Publication No. 2006-191236).
The rolling shutter scheme denotes a scheme where pixels outputting signals perform photoelectric conversion from the time of outputting the signals and perform accumulation of signal charges in a photodiode until the reading is sequentially performed. In this scheme, accumulation time intervals for the signal charges are different according to the rows in the pixel array. Therefore, deformation exists in the captured image.
On the other hand, the global shutter scheme denotes a scheme of sustaining concurrency of the accumulation time intervals for the signal charges in order to remove the deformation caused by the rolling shutter scheme. In order to implement the global shutter scheme, there have been proposed a method of additionally using a mechanical shutter (refer to Japanese Unexamined Patent Application Publication No. 2006-191236), a method of sustaining concurrency of the accumulation time intervals by performing the transfer of signal charges from photodiodes simultaneously at all pixels in a floating diffusion covered by a light shielding layer and storing the signal charges until the reading is performed (refer to Japanese Unexamined Patent Application Publication No. 2009-049870) and the like.
In the structure of the CMOS type image capturing device shown in FIG. 1 in the related art, Japanese Unexamined Patent Application Publication No. 2001-028433 discloses that crystal defect is easily introduced in an end portion of a transfer gate TG formed by anisotropic etching with respect to Poly-Si (polysilicon) or the like. In the off state of the transfer gate TG, due to a voltage difference between the floating diffusion FD and the transfer gate TG, the electric field concentration occurs in the vicinity of the end portion of the transfer gate TG where the crystal defect is easily generated. As a result, a leak current is generated through the crystal defect at the site of the electric field concentration, so that aliasing signals may be output at a dark time or a low luminance time.
In addition, in FIG. 1, an n type impurity diffusion layer n1 is disposed as a first conduction type semiconductor layer on a silicon substrate Si, and a p type impurity diffusion layer p1 is disposed as a second conduction type semiconductor layer thereon. The photodiode PD is constructed with the layers p1 and n1. In addition, in the figure, an element isolation region DV is disposed, and under the element isolation region DV, a p type impurity diffusion layer p2 is disposed. In addition, an n type impurity diffusion layer n2 is disposed opposite to the photodiode PD with the transfer gate TG interposed therebetween, so that the floating diffusion FD is formed.
More specifically, in general, in a semiconductor apparatus, according to a mechanism called a Trap-Assisted-Tunneling (TAT) model, it is described that, if electric field concentration occurs in a crystal defect portion due to a reverse bias of a pn junction, a leak current is generated through the crystal defect. In addition, it is widely known that the aforementioned problem occurs due to the similar mechanism (refer to Hurkx et al., “A New Recombination Model for Device Simulation Including Tunneling” (IEEE TED. Vol. 39, no. 2, pp. 331-338, 1992) and G. Eneman et al., “Analysis of junction leakage in advanced germanium P+/n junctions” (in Proc. European Solid-State Device Research Conf. 2007, pp. 454-457)).
FIGS. 2A and 2B illustrate simulation results of an impurity concentration distribution and an electric field strength distribution of the floating diffusion region in the CMOS type image capturing device in the related art. FIG. 2A illustrates the impurity concentration distribution, and FIG. 2B illustrates the electric field strength distribution. In the impurity concentration distribution of FIG. 2A, as the color is closer to white, the concentration of the n type impurities is higher; and as the color is closer to black, the concentration of the p type impurities is higher. In addition, in the electric field strength distribution of FIG. 2B, as the color is closer to white, the electric field strength is higher; and as the as the color is closer to black, the electric field strength is lower. In addition, FIGS. 2A and 2B illustrate the case where the transfer gate TG exists and the floating diffusion FD is disposed in the figures. In other words, FIGS. 2A and 2B illustrate the distributions in the enlarged range of the vicinities of the transfer gate TG and the floating diffusion FD of FIG. 1. In FIG. 2B, an off time of the transfer gate TG is assumed, and thus, a negative voltage is applied to the transfer gate TG, so that the floating diffusion FD region is at a positive voltage.
In other words, in the case of a structure shown in FIGS. 2A and 2B in the related art, at the off time of the transfer gate TG, a negative voltage is applied to the transfer gate TG, so that the voltage may be transferred through a gate insulating layer to an inner portion of the silicon substrate Si just under the gate insulating layer. As a result, due to a voltage difference between the silicon substrate just under the gate insulating layer and the floating diffusion FD region, there exists an area (area A in FIG. 2B) in the vicinity of the end portion of the transfer gate TG, where the electric field has the maximum value.
Particularly, in the global shutter scheme CMOS type image capturing device, in the case where signal charges are stored in the floating diffusion FD in an example such as Japanese Unexamined Patent Application Publication No. 2006-311515, the influence of the leak current is inevitable. In other words, during the signal charge storing time interval, since the leak current is continuously generated in the floating diffusion FD due to the aforementioned mechanism, noises occur in the to-be-transferred signal charges, so that an SN ratio (signal to noise ratio) deteriorates.
Therefore, it is preferable to obtain a structure of reducing the leak current by implementing a structure of allowing no electric field concentration to occur in an area such as an end portion of the transfer gate TG where the crystal defect is easily generated.